As semiconductor devices have become more highly integrated in recent years, circuit interconnections have become finer and distances between those interconnections have become smaller. In case of photolithography, which can form interconnections that are at most 0.5 μm wide, it is required that surfaces on which pattern images are to be focused by a stepper should be as flat as possible because a depth of focus of an optical system is relatively small. A polishing apparatus for performing chemical mechanical polishing (CMP) has been used as means for planarizing a surface of such a semiconductor wafer.
This type of chemical mechanical polishing (CMP) apparatus comprises a polishing table having a polishing cloth thereon and a top ring. An abrasive liquid is supplied onto a surface of the polishing cloth while a workpiece (wafer) is interposed between the polishing table and the top ring. At the same time, the workpiece is pressed against the polishing table by the top ring to polish a surface of the workpiece to a flat mirror finish.
Recently, there has been known a polishing apparatus having a plurality of polishing units including a polishing table and a top ring. In such a polishing apparatus, receiving/delivering mechanisms (pushers) for receiving and delivering a wafer are provided at wafer receiving/delivering positions for respective top rings, and a transfer robot is provided to transfer a wafer between these pushers.
However, in the aforementioned polishing apparatus, since each polishing unit requires a pusher, a large space is required for installing the pushers. Further, a large space is required for moving the transfer robot to transfer the wafer between the pushers, and thus the apparatus becomes larger. Further, because the transfer robot cannot transfer a plurality of wafers at the same time, transfer of a target wafer may be delayed when the transfer robot is used to transfer another wafer in a case where the transfer robot is employed for various purposes. In such a case, processing and transfer of wafers cannot be performed efficiently, so that throughput is lowered.